Digital to analog converters (DACs) and analog to digital converters (ADCs) are used in a variety of applications. In performing the conversion, the DAC/ADC typically uses techniques such as ΔΣ conversion to find a closest match to the input signal and convert errors to out-of-signal band noise. The requirements of such DACs/ADCs may be quite stringent for certain applications. For example, DACs and ADCs may be used in modern audio systems. For such applications, the targeted performance may be a signal-to-noise ratio (SNR) of sixteen bits, or higher in certain bandwidths such as the 20 kHz audio bandwidth. Similar technologies, for example, third generation cellular phone and voice over Internet protocol (VOIP) audio conferencing phones, also require high performance audio coder/decoders (CODECs) that are low in cost but which do not unduly sacrifice performance. Although DACs and ADCs are known, conventional used in converting errors, such as data weighted averaging, may not be adequate for certain applications or may be expensive to implement. Consequently, a mechanism for providing low cost, high-performance data converters is desired.
Dynamic element matching (DEM) is a technique that may be used in converting mismatch errors into out-of-signal band noise for ADCs/DACs. Implementing DEM might be relatively low in cost because DEM does not require highly accurate calibration systems. In order to perform DEM, vector quantization is used. Vector quantization is a mathematical technique that may be used to shape the analog mismatch noise out of the signal band, allowing the DAC/ADC to perform its function. In particular, vector quantization determines a closest match to a particular vector. In an implementation of an ADC/DAC using DEM, vector quantization might be used to determine how to switch the DAC/ADC elements, such as capacitors and current sources, to find the closest match to an input signal.
To more readily understand vector quantization, refer to FIG. 1, which is a diagram 10 depicting three-dimensional vector quantization. The vector U 12 corresponds to the input signal. Thus, U 12 corresponds to a sample of the input signal. Mathematically, vector quantization determines the vector that is closest match to the vector U 12 and that has unit vector components in each dimension. Stated differently, for the three-dimensional case depicted in FIG. 1, vector quantization would determine the projection of the vector U 12 onto the closest vector defined by the origin (0,0,0) and the vertices of the cube 14. Consequently, the output of the vector quantization would be a vector that is zero or is from the origin (0,0,0) to one of the vertices (1,0,0), (0,1,0), (0,0,1), (1,1,0), (0,1,1), or (1,1,1). The closest match between U 12 and the output, V, occurs when ∥U−V∥ is minimized. This quantity is minimized when the scalar product of U 12 and V is maximized, which corresponds to U 12 being aligned with V. Aligning U 12 and V thus corresponds to identifying the largest elements of the U 12. Thus, using mathematical techniques, vector quantization may find the closest match to U 12 as well as the error.
In applications of vector quantization, the number of spatial dimensions corresponds to the desired resolution. The desired resolution, R, is given by the desired number of bits in the resolution. The number, N, of spatial dimensions of the vector U corresponding to the input signal is greater than or equal to 2R−1. Thus, for a two bit resolution, the number of spatial dimensions is three. Consequently, the cube 14 depicted in FIG. 1 might be used in performing vector quantization for applications having a three bit resolution requirement. For four-bit resolution, the number of spatial dimensions is 15. For higher resolution, the number of dimensions scales exponentially.
Although DEM may be lower in cost to implement, there are currently barriers to its use in conventional DACs/ADCs. In particular, implementing vector quantization may have undesirable results. Signals are desired to have n-bit resolution (an n-bit signal), for example in N-bit ΔΣ conversion. In such a conversion, the corresponding vector has N dimensions (corresponding to 2n−1, as discussed above). Stated differently, vector quantization would take place in N dimensions, where N is 2n−1. The conventional vector quantizer would, therefore, sort approximately 2n elements for each input data sample. This sorting operation typically requires a clock that runs 2n times faster than the sampling clock used in obtaining the data sample. Such a clock would be very high frequency, which would be undesirable. Furthermore, the DAC/ADC would include at least two clocks, the sampling clock and the clock used in sorting. Consequently, the DAC/ADC would also be a mixed mode environment. Use of a high frequency clock in a mixed mode environment is also undesirable.
Accordingly, what is needed is a mechanism for aiding in providing high speed, low cost converters. The present invention addresses such a need.